Non-volatile semiconductor memory cells permitting charge storage capability are well known in the art. The charges are typically stored in a floating gate to define the states of a memory cell. One such non-volatile memory cell has been proposed in U.S. application Ser. No. 09/942,338, which is hereby incorporated by reference.
The present invention can best be understood with an understanding of how the memory cells in prior art are constructed and how they are operated.
FIG. 1 (prior art) shows a cell architecture 100, wherein there is a tunneling gate 10, a ballistic gate 12, a floating gate 14, a source 16 and a drain 18 with a channel 20 therebetween, and a body 22 in a substrate of a first conductivity type (e.g. p-type). The ballistic gate 12 can be also termed as grid gate. However, term “ballistic gate” is preferable due to its nature on passing ballistic charge, and is employed hereinafter. The source 16 and drain 18 are formed in the substrate and have a second conductivity type (e.g. n-type). The floating gate 14 is disposed over and insulated from the channel 20 by a floating gate dielectric 24. The ballistic gate 12 is disposed over and insulated from the floating gate 14 by a retention dielectric 26. Likewise, the tunneling gate 10 is disposed over and insulated from the ballistic gate 12 by a layer of tunneling dielectric 28. A dielectric filler 29 is disposed around floating gate 14 and having its top surface be coincident with the top surface of the ballistic gate 12.
Ballistic hot hole and hot electron are injected into floating gate of prior art memory cells for erase and program operations, respectively, through injection mechanism first illustrated in the tunnel emission amplifier (see Mead, “The Tunnel Emission Amplifier,” Procedings of the IRE, vol. 48, pp. 359–361, 1960). FIG. 2A (prior art) illustrates the ballistic hot hole injection of such mechanism in together with the energy band diagram for regions from tunneling gate 10 to floating gate 14 along a vertical axis (not shown) in cell 100. The tunneling gate 10 is biased positively with respect to the ballistic gate 12 to permit holes 30 in the tunneling gate 10 to tunnel through a tunneling barrier having a valence band barrier height 32 between a valence band 10b of the tunneling gate 10 and a valence band 28b of the tunneling dielectric 28. These holes in the ballistic gate region 12 can transport at energy higher than the valence band 12b of that region with some of these holes being able to reach the interface between the ballistic gate 12 and the retention dielectric 26. When this positive bias is increased to a value such that those holes have energy higher than a hole barrier height 34 at the interface, the holes will be able to enter a valence band 26b of the retention dielectric region 26, making their way through that region and be collected on the floating gate 14. To complete the erase operation, a sufficient amount of holes must be injected onto the floating gate 14 to neutralize negative charges thereon.
The ballistic hot electron injection for programming prior art memory cell is done similarly to the ballistic hot hole injection except by reversing the bias polarity. Referring to FIG. 2B (prior art), the tunneling gate 10 is biased negatively with respect to the ballistic gate 12 to permit electrons 31 in the tunneling gate 10 to tunnel through the tunneling dielectric 28. These electrons in the ballistic gate region 12 can transport at energy higher than a conduction band 12a of that region with some of these electrons being able to reach the interface between the ballistic gate 12 and the retention dielectric 26, surmounting an electron barrier 35 and entering the floating gate 14.
The charge injection mechanism employed in prior art is the same mechanism illustrated for amplifier application (see Mead, “The Tunnel Emission Amplifier,” Procedings of the IRE, vol. 48, pp. 359–361, 1960). However, there are several fundamental problems associated with the charge injection mechanism when such mechanism is employed for memory operation. Further, there are several problems in the prior art memory cell need to be considered.
Problems on Charge Injection Mechanism of Prior Art
It is known that there are various types of holes, namely the light-hole (LH) and the heavy-hole (HH), in semiconductors (e.g. Si, Ge, GaAs etc.). The light-hole has a lighter effective mass than the heavy-hole, and difference between them depends on the band structure of the valence sub-bands of semiconductors. Prior art did not distinguish these two different types of holes while employing ballistic hole injection mechanism for erasing prior art memory cells. Further, the prior art did not teach the effects associated with these two types of holes on the injection mechanism. Thus, the injection scheme employed in prior art is believed to suffer from following problems:
1) Low Injection Efficiency
It is known that the population of holes in a semiconductor is primarily of the heavy-hole (HH). This is to first order due to its larger density-of-state effective mass. For example, in silicon, it is known the HH occupied about 80 percent of the total population of holes (see, for example, Fischetti et al., Journal of Appl. Physics, vol. 94, pp. 1079–1095, 2003). Further, it is known the ballistic carrier transport is characterized by its mean-free-path, where a ballistic carrier having a longer mean-free-path can transport a longer distance without scattering. The mean-free-path is approximately inversely proportional to the mass of the carriers. Therefore, HH typically has a shorter mean-free-path, and are more likely to experience scattering events through interacting with other types of carriers (e.g. phonons). Thus, a ballistic HH is more prone to loose its ballistic nature during its transport in a semiconductor region. When a ballistic HH transports at energy greater than its thermal energy, it is therefore more likely to loose its energy to become a thermal carrier. Even not loosing all its energy, HH can have its energy component in the direction to the floating gate region (or targeted destination) be significantly lowered such that the hole has insufficient energy to surmount the barrier height 34 of the insulator 26. In other words, when ballistic holes are employed for erasing prior art memory cells, since the majority population of the hole carriers are of the HH type, which has a shorter mean-free-path, most of the supplied holes cannot contribute to the erase operation as anticipate. This causes waste on total current. The combined effects of population and effective mass result in the ballistic hole injection efficiency significantly lower than one usually can expect. (Here, the efficiency is defined as number of charges injected compared to total number of charges supplied).
2) Higher Power Consumption and Slower Erase Speed
The aforementioned effects were ignored in prior art memory cells, and hence the cells require more electrical current be supplied, thus consuming more electric power, in order to complete an erase operation. Further, the low hole injection efficiency in prior art cells can result in slow erase problem when implementing the cells in their product applications.
Problems on Parasitic-Electrons Backward Injection
Please refer to FIG. 3A on this problem. FIG. 3A is similar to FIG. 2A except with additional parasitic electrons 36 and 37 in the valence band 12b and conduction band 12a, respectively. The electrons 36 and 37 are also known as the valence electrons 36 and the conduction electrons 37, respectively. Both electrons 36 and 37 are shown transporting along a backward direction (hereinafter “backward injection”) from ballistic gate 12 to tunneling gate 10 when holes 30 are injected from tunneling gate 10 to ballistic gate 12 along a forward direction (hereinafter “forward injection”) for erase operation. To suppress these parasitic electrons, prior art taught requirement on material for ballistic gate 12, where material with larger work function, such as a heavily doped p-type polysilicon (“p+ polysilicon”), is required. P+ polysilicon is taught in the prior art because electrons 37 in that material is usually negligible. Further, prior art taught a symmetrical tunneling stack structure comprising tunneling gate 10, tunneling dielectric 28, and ballistic gate 12, wherein tunneling gate 10 and ballistic gate 12 are of p+ polysilicon. The tunneling dielectric 28 is constructed in a single layer of oxynitride with oxide fraction engineered at level less than about 77% such that current flow of the backward injected electrons can be kept at similar current level as that of the forward injected holes 30. In other words, the current of backward injected electrons in prior art cell cannot be entirely suppressed. This causes waste on total current as the forward injected charge and its current is the one of interest for cell operations. Further, there are several other fundamental deficiencies on the symmetrical tunneling structure and cell structure of prior art. The issue is described next with reference to FIGS. 3A and 3C.
Referring to FIG. 3A, for ballistic gate 12 of a p+ polysilicon in prior art, electrons 37 in that region is usually negligible when a low voltage is applied between tunneling gate 10 and ballistic gate 12. Therefore, tunneling current of electrons 37 is negligible. The parasitic electrons thus mainly comprise electrons 36 of valence band 12b and are tunneled to tunneling gate 10 through a trapezoidal-shaped barrier (also known as “direct tunneling”). However, when a voltage of erase operation (e.g. 5V) is applied between tunneling gate 10 and ballistic gate 12, the portion of ballistic gate 12 next to tunneling dielectric 28 can be inadvertently inverted and thus a layer of electrons 37 can still be formed therein. The electrons 37 are formed near the interface between tunneling dielectric 28 and ballistic gate 12 and can be emitted into tunneling gate 10 along path 37a to become hot electrons having energy higher than a minimum of conduction band 10a of that region. The tunneling is through a triangle-shaped tunneling barrier (also known as “Fowler-Nordheim tunneling”) having a barrier height 33 that is lower than that of electrons 36 by an energy gap 12c of the ballistic gate 12. Therefore, due to the lower barrier height and the triangular shaped barrier for electrons 37, a much stronger tunneling current is expected once tunneling process for electrons 37 starts. FIG. 3C illustrates the parasitic currents JCE and JVE, associated with conduction electrons (“CE”) 37 and valence electrons (“VE”) 36, respectively. The voltage dependence of current JCE is seen much stronger than that of current JVE due to the much stronger dependence of current on voltage when charges tunneling through a triangle-shaped barrier. Parasitic current JCE is seen dominating the total current in the higher voltage range (e.g. about 5V). The results show that electrons 37 dominate the parasitic electrons 36 in valence band 12b and hence the total parasitic electrons tunneled into the tunneling gate 10. Note that this effect is work function independent. The p+ polysilicon/oxynitride/p+ polysilicon tunneling stack in prior art overlook such effect, and hence the prior art cell 100 can suffer from the parasitic carriers backward tunneling. Therefore it cannot function properly.
Problems on Parasitic-Holes Backward Injection
Parasitic holes backward injection problem is another major problem for the mechanism employed in prior art. Please refer to FIG. 3B on this problem. FIG. 3B is similar to FIG. 2B except with additional parasitic holes 38 shown in the valence band 12b and some others elements (e.g. electrons 40 and 40′) to be discussed in a later session. Holes 38 are shown transporting in the backward direction from ballistic gate 12 to tunneling gate 10 when electrons 31 are injected in the forward direction for program operation of prior art cell. The problem on backward injected holes 38 is caused by the requirement on higher work function in prior art. Further there are shown barrier height 10c for forward injected electrons 31, and barrier height 39 for backward injected holes 38. Referring to FIG. 3B, as work function of the ballistic gate 12 is increased, once it's beyond a level where the barrier 39 becomes less than the barrier height 10c, parasitic holes 38 can be backward injected to tunneling gate 10 and can result in problems to the program operation similar to that caused by the parasitic electrons to the erase operation. Therefore, the symmetrical tunneling structure of prior art cannot be optimized to suppress parasitic charge carriers for both program and erase operations simultaneously. Such problem prevents tunneling gate 10 in the prior art cell from being used as a single electrode for supplying both types of charges (i.e. electrons and holes). Therefore, it is believed prior art require two separate tunneling gates: one for electron tunneling injection, and the other one for hole tunneling injection. This requirement results in larger cell size, and limits the cell of prior art from practical application.
Problems on Impact Ionization
In addition to the problems described above, the injection mechanism and energy band structure employed in prior art also can suffered from impact ionization problem. FIG. 3B shows the impact ionization problem in the prior art band structure in FIG. 2B. There are shown electrons 40 in the conduction band 10a of tunneling gate 10. In the program operation of prior art, a typical voltage of −2 V and a +2 V is applied to the tunneling gate 10 and ballistic gate 12, respectively. The voltage difference between these gates has to be greater than a minimum voltage in order to supply sufficient energy for electrons 31 (see FIG. 3B) to surmount the barrier height 35 to enter the floating gate 14. However, due to the high bias thus introduced across tunneling dielectric 28, an inversion layer of electrons 40 can be formed in the conduction band 10a of the tunneling gate 10 of p+ polysilicon. Further, another mechanism that can form electrons 40 is through the impact generation process triggered by the backward injected holes 38. As is clearly shown in FIG. 3B that as these holes 38 enter into tunneling gate 10, their energy can be high enough to generate, through impact ionization process, secondary electrons 40 in conduction band 10a or energetic electrons 40′ having energy higher than conduction band 10a. These conduction electrons 40 and 40′ thus generated are termed “Impact-Ionized CE” and behave very differently than the electrons 31 at the valence band 10b. Similar to that illustrated in FIG. 3C, in such range of bias, the current of CE (JCE) is much larger than the current of VE (JVE). In other words, the generated CE 40 and 40′ (either through inversion or through impact-ionization) can dominate the tunneling current between tunneling gate 10 and ballistic gate 12 of prior art.
Likewise, impact ionization problem can also happen in ballistic gate 12 and can be triggered by electrons 40 or by energetic electrons 40′ transported from tunneling gate 10. As described above, these electrons 40 and 40′ are inadvertently generated under the bias condition for program operation. The presence of these electrons is not desirable as they carry a much higher energy than that carried by the electrons 31. As illustrated in FIG. 3B, these electrons 40 and 40′ can tunnel through the tunneling dielectric 28 at such a high energy into ballistic gate 12 and subsequently causes impact ionization therein, where pairs of electrons 40b and holes 40a are created.
It is now clear that the impact ionization and the inversion layer formation can exist in the tunneling gate 10 in the energy band structure for the ballistic injection scheme of prior art. All these effects can create parasitic electrons 40 and 40′ in tunneling gate 10. The effects and the parasitic electrons in the tunneling gate region 10 were not taken into account in the prior art. These effects are uncontrollable, where current can unduly increase to result in current loading issue on supporting circuitry for memory operations. To avoid these problems in program operation, the allowable maximum voltage between gates 10 and 12 has to be limited under a threshold voltage to avoid the formation of electrons 40 and/or 40′ in tunneling gate 10. The range between the minimum and the maximum program voltages defines a workable voltage range for program operation of prior art, and is quite narrow for the injection mechanism employed in prior art (less than about 0.6V). The cell structure in prior art thus demands stringent control on the threshold voltage, and is believed having low manufacturability yield and difficulties in practical applications.
Similar to the program operation, in the erase operation (referring to FIG. 3A), the impact-ionization process can also occur in tunneling gate 10 due to electrons 37 backward injected from ballistic gate 12. The backward injected electrons 37 have an energy high enough to impact ionized charge carriers in tunneling gate 10 to cause loading issue on supporting circuitry for memory operations. The injection mechanism, energy band and cell structure in prior art thus face similar issues in both the program and the erase operations, and the memory is believed having low manufacturability yield and difficulties in practical applications.
Problems on Dielectric Breakdown
Please refer to FIG. 2A for the illustration. In the erase operation of prior art, a typical voltage of +2.5 V and a −2.5V is applied to tunneling gate 10 and ballistic gate 12, respectively. The voltage difference between these two gates has to be greater than a minimum voltage in order to supply sufficient energy for holes 30 to surmount the barrier height 34. However, for the energy band structures proposed in the prior art, such voltage results in a maximum field in the range of about 10 MV/cm to about 20 MV/cm across the tunneling dielectric layer 28. In such range of high field, the tunneling dielectric 28 is believed suffered from dielectric breakdown (see FIG. 3C). To avoid a dielectric breakdown event in cell operation, the maximum allowable voltage between gates 10 and 12 has to be limited under the dielectric breakdown voltage. The range between the minimum and the maximum voltages defines a workable voltage range for the erase operation, and is quite narrow in prior art (typically less than about 0.7V). The cell structure in prior art thus demands stringent control on the dielectric breakdown, and is believed having difficulties in practical applications.
Problems on Parasitic Capacitance
In the energy band structure and cell structure of prior art, the thickness of the tunneling dielectric layer 28 is chosen with a limitation typically in the range of about 2 nanometer to 4 nanometer (“nm” hereinafter) in order to permit charge carriers tunneling through that layer. Therefore, it results in a large parasitic capacitance C between gates 10 and 12, and is undesirable as it introduces adverse impact on cell operation. The capacitance issue can be better understood by referring to the diagram in FIG. 3D (prior art), wherein CBG-TG is the capacitance between ballistic gate 12 and tunneling gate 10, and CBG-FG is the capacitance between ballistic gate 12 and floating gate 14. The total capacitance seen by ballistic gate 12 comprises two main components shown in FIG. 3D, and approximately equals the summation of CBG-FG and CBG-TG. In most situations, the total capacitance can be dominated by CBG-TG due to the much thinner thickness for the tunneling dielectric layer 28 than that for the retention dielectric layer 26, which is typical in the range of about 7 nm to about 12 nm. The capacitance issue is worse when employing dielectric with higher dielectric constant (e.g. oxynitride), which is provided in the prior art for suppressing the parasitic electrons in ballistic gate 12 during hole injection for the erase operation. Therefore, the cell architecture in prior art further suffer from the compromise between suppressing the parasitic electrons and suppressing the total capacitance of ballistic gate 12.
Problems on Large Resistance
In the prior art, ballistic gate layer 12 is desirable to be with a thickness in the range of a few times of the mean-free path of carrier scattering (typically in the range of 10–20 nm), in order to permit the injected carriers transporting through ballistic gate 12 with good efficiency. The needs on a thin thickness unavoidably results in a high sheet resistance to that layer. As described earlier, to reduce parasitic electron tunneling (see FIG. 3A), prior art is limited to using p-type Si for both tunneling gate 10 and ballistic gate 12 when polysilicon is used as the material for these gates. It is known that a heavily doped p-type polysilicon (“p+ polysilicon”) typically has a higher resistivity than that of a heavily doped n-type polysilicon (“n+ polysilicon”). Therefore, prior art suffers from a much larger resistance R on both tunneling gate 10 and ballistic gate 12.
The adverse effect of a large R on memory cell performance can be understood from several directions. First, it can cause a large signal delay due to the combining effects of the large R and the large C (i.e. the RC delay). This is particularly a main issue on cell operation as the RC delay can limit the speed on accessing a memory cell when embedded in a large memory array. Secondly, for disturb prevention on un-selected cells, an optimum set of predetermined voltages usually are required to be applied to those cells. However, due to the RC delay, voltages on un-selected cells can be different than the desired values, and hence cell disturb is more prone to happen. Furthermore, the large R can combine with a large current I to result in a IR effect, which can cause a voltage drop when passing a voltage in a signal line. The effect prevents the voltage on a designated electrode of a memory cell from reaching its desired level, and hence can adversely impact cell operation. For example, the adverse impact on an un-selected cell can be an undesired cell disturb, where the cell state is unintentionally changed from one logic state (e.g. a “0”) to the other (e.g. a “1”). The IR impact on a selected cell can be a slower speed on cell operations (i.e. program, erase, and read operations).
Problems on Weak Voltage-Dependence of Tunneling Current
The energy band structure in prior art is constructed to permit charge carriers of one type tunneling from tunneling gate 10 to ballistic gate 12 at a current level similar to that for the backward injected parasitic electrons. This results in weak voltage-dependence on the current-voltage relationship. For example, the current for an erase disable condition (i.e. the condition to prevent an unselected cell from an erase disturb) is seen only 104 times lower than that for the erase condition. Similar results can be seen in the program disable condition of prior art. Therefore, unselected cells in prior art are prone to cell disturb issues in both program and erase operations.
These problems can be overcome in accordance with one aspect of the present invention by providing a piezo-ballistic-charge-injection mechanism. Employing the mechanism, the present invention further provides technique altering effective mass of ballistic charge carriers and hence its mean-free-path. Additionally, employing the mechanism, the present invention provides technique increasing carriers population in sub-bands or valleys favorable to their transport. The piezo-ballistic-charge-injection mechanism is implemented in cell structures in accordance with the present invention. Further, these problems can be overcome in accordance with another aspect of the present invention by providing a barrier height engineering concept on energy band structure, by providing a novel method altering barrier heights, by providing injection filter structures, and by providing new cell structures.